Wafer-level reliability testing may include simultaneous testing of large numbers of devices under test (DUTs) that are present on a wafer, or substrate. Probe head assemblies that are utilized to perform wafer-level reliability testing may include a plurality of probe heads, with each probe head including one or more probe tips configured to contact a corresponding contact pad of a corresponding DUT.
Wafer-level reliability tests often may be performed at elevated temperatures and/or over a range of test temperatures. In general, a coefficient of thermal expansion of the probe head assembly may not be matched, or identically matched, to a coefficient of thermal expansion of the substrate. Thus, changes in test temperature may lead to differences in a spacing of the probe heads, or the probe tips thereof, when compared, or relative, to a spacing of the DUTs, or the contact pads thereof. In addition, the substrate also may distort, twist, and/or deform during heating and/or cooling thereof, thereby changing a distance between a region of the probe head assembly and the substrate relative to a distance between another region of the probe head assembly and the substrate.
In order to permit testing despite this spacing difference, probe head assemblies may be designed such that the spacing of the probe heads matches the spacing of the DUTs at one temperature, such as a design temperature. In addition, the contact pads of the DUTs may be oversized to accommodate at least a threshold spacing difference, such as may be expected and/or encountered over a given test temperature range.
While such an approach may be effective at permitting the wafer-level reliability tests to be performed, the oversized contact pads may consume valuable space on the surface of the DUT, and it may be desirable to decrease the size of the contact pads. Additionally or alternatively, a contact pad size necessary to permit testing over a desired temperature range may be prohibitively large, especially for test structures that may be positioned within scribe lines between adjacent DUTs. Thus, there exists a need for improved probe systems, storage media, and methods for wafer-level testing over extended temperature ranges.